Reliably producing sub-half micron and smaller features is one of the key technology challenges for next generation very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of VLSI and ULSI technology have placed additional demands on processing capabilities. Reliable formation of gate structures on the substrate is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design have resulted in the development of three dimensional designs, such as fin-like field effect transistors (FinFETs). A typical FinFET is fabricated with a fin structure extending from a substrate, for example, by etching into a silicon layer of the substrate. The channel of the FinFET is formed in the vertical fin. A gate structure is provided over (e.g., overlying to wrap) the fin structure. It is beneficial to have a gate structure on both sides of the channel allowing gate control of the channel from both sides. FinFET devices provide numerous advantages, including reduced short channel effects and increased current flow.
As the device dimensions continue scaling down, existing device structures may not be satisfactory in all aspects. Photolithography limitations often constrain the process capability to provide gate structures with smaller dimensions. Thus, FinFET device structures with desired adjustable or decreased gate dimensions are considered and desired to provide the device structures with desired electrical performance.